U.S. Pat. No. 6,903,571 describes a field programmable gate array (FPGA) with routing multiplexers to provide connections in a matrix of programmable cells. Conventionally a rectangular matrix is used, with rows and columns of programmable cells. Each cell may contain a logic circuit containing one or more lookup table memories, that stores programmed responses to different combinations of input signal values.
The input signals of the logic circuit of a cell may come from other cells in the matrix. Conventionally such signals are often routed along a “Manhattan routing pattern”, which means that the signal route first runs along the direction of a column or row and at a selected cell turn a corner to be routed along a row or column, orthogonally to the original column or row and so on.
The connection route is defined by programmable routing multiplexers. Each cell contains a number of routing multiplexers that are used to supply selected signals to the inputs of the logic circuit of the cell and also to forward signals from a first other cell to a second other cell, for example at a position where the route from the first other cell to the second other cell turns a corner.
In known FPGA's the inputs of routing multiplexers of a cell may be connected to outputs of routing multiplexers of neighboring cells in the matrix, or to global bus conductors that run along an entire row or column of the matrix. However, it has been found that this way of providing signal routes may lead to inefficient use of cells in a matrix of programmable cells.